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FPGAs for Beginners
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

Hi, I'm Stacey, and in this video I discuss AXI! Here's part 2 https://youtu.be/y0z5Cg4gp6k Github Code ...

17:40
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

37,620 views

2 years ago

Arm®
The AXI Protocol

The Advanced eXtensible Interface (AXI) protocol is a point-to-point interface specification for masters and slaves. This video ...

0:47
The AXI Protocol

39,753 views

5 years ago

People also watched

VerifSudha
Master AXI protocol: AXI WRITE 2 Byte length (4KB crossing)

Have you ever come across phrases like 'A burst must not cross a 4KB address boundary' or 'write transactions with the same ...

11:51
Master AXI protocol: AXI WRITE 2 Byte length (4KB crossing)

7,833 views

2 years ago

Microelectronic Systems Design Research Group
AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

The Xilinx ZYNQ Training Video-Book, will contain a series of Videos through which we will make the audience familiar with the ...

1:52:36
AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

121,350 views

11 years ago

Peikm
Creating a custom AXILite IP in Vivado 2020.1

How to create a custom AXILite IP in Vivdado 2020.1 and test it on a Pynq-Z2 board using Python MMIO library. A link to the ...

11:10
Creating a custom AXILite IP in Vivado 2020.1

2,110 views

4 years ago

biquinary
AXI Stream Tutorial

A quick AXI Stream tutorial I recorded with absolutely no preparation. Sorry if it's crappy.

9:22
AXI Stream Tutorial

17,537 views

5 years ago

anurag choudhury
Microblaze RTL Simulation and AXI Slave wrapper tutorial

This video demonstrates how to run C code on Microblaze without using FPGA by associating the ELF file(generated by Xilinx ...

29:00
Microblaze RTL Simulation and AXI Slave wrapper tutorial

9,683 views

5 years ago

Noah De Los Santos
Vivado Tutorial: Turn Verilog IP into AXI Module

This video describes an overview of how I converted my Verilog IP into an AXI module in Vivado so I could test my design.

29:24
Vivado Tutorial: Turn Verilog IP into AXI Module

10,546 views

5 years ago

MASTER VLSI
AXI PROTOCOL - 2

The AXI (Advanced eXtensible Interface) protocol is a standard for high-performance communication between components within ...

1:55:13
AXI PROTOCOL - 2

10,653 views

1 year ago

FPGAPS
Xilinx MIG DDR3 Interface: Read and Write using AXI traffic Generators

Read and write data to the external DDR3 using MIG and Axi Traffic generator. The presenter walks through the entire process ...

8:36
Xilinx MIG DDR3 Interface: Read and Write using AXI traffic Generators

3,172 views

7 months ago

VLSIGuru - Best VLSI Training Institute
AXI SES1 14JUN2023.mp4

Agenda:

1:49:59
AXI SES1 14JUN2023.mp4

7,187 views

2 years ago

FPGAPS
AXI DMA and debugging with ILA, part 1: Vivado design

implementation of AXI Direct Memory Access (DMA) in FPGA design using Vivado. The video begins with a detailed explanation ...

14:36
AXI DMA and debugging with ILA, part 1: Vivado design

5,143 views

1 year ago

Renzym Education
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]

AXI #AXIstream #AXIMM AMBA AXI Memory Mapped and AXI streaming Interfaces. AXI MM and AXI streaming interfaces are ...

18:56
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]

26,061 views

3 years ago

SiliconAdda
Introduction to Axi4

#Axi protocol #axi #Axi4 #vlsiprojects #vlsi #vlstudies #vlsitraining #amba #Arm #design verification #amba #arm #digital design ...

41:27
Introduction to Axi4

6,971 views

1 year ago

Dillon Huff
What is AXI (Part 1)

In this video I give a brief overview of the AXI protocol.

7:04
What is AXI (Part 1)

113,899 views

6 years ago

FPGAs for Beginners
AXI Stream basics for beginners! A Stream FIFO example in Verilog.

Hi, I'm Stacey, and in this video I go over the basics of the AXI stream interface. HDLforBeginners Subreddit!

12:11
AXI Stream basics for beginners! A Stream FIFO example in Verilog.

45,789 views

4 years ago

Semi Design
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program

Points of XI that is removed for xi4 and some new things were added okay so before that okay let me start with XI protocol and its ...

47:57
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program

9,643 views

1 year ago

ALL ABOUT VLSI
Introduction to AXI Protocol | AXI Channels Explained | In-Order vs Out-of-Order Transactions

In this video, we dive into the AXI (Advanced eXtensible Interface) Protocol, one of the most widely used AMBA bus protocols in ...

19:52
Introduction to AXI Protocol | AXI Channels Explained | In-Order vs Out-of-Order Transactions

3,846 views

1 month ago

ALL ABOUT VLSI
AXI Protocol Explained: Signal and Channel Descriptions | AXI Read & Write Channels Made Easy

In this video, we'll dive deep into the AXI (Advanced eXtensible Interface) protocol — focusing on signal descriptions and channel ...

26:43
AXI Protocol Explained: Signal and Channel Descriptions | AXI Read & Write Channels Made Easy

1,532 views

1 month ago

ALL ABOUT VLSI
AXI Write and Read Transfer | Beginner-Friendly AMBA Protocol Tutorial || All about VLSI ||

In this video, we break down the basic Write and Read Transfer operations in the AMBA and AXI protocols, two of the most widely ...

25:16
AXI Write and Read Transfer | Beginner-Friendly AMBA Protocol Tutorial || All about VLSI ||

1,004 views

1 month ago

Electronics & VLSI Projects
What is AMBA - AXI part 1

axi #amba_axi #amba #vlsi #system_verilog #system-verilog #uvm #system-verilog-coding #vlsi_design_verification #verilog We ...

9:05
What is AMBA - AXI part 1

26,529 views

5 years ago

IIT Madras - BS in Electronic Systems
W1L5 - AXI Bus Protocol Overview

W1L5 - AXI Bus Protocol Overview Prof. Nitin Chandrachoodan Department of Electrical Engineering Indian Institute of ...

33:57
W1L5 - AXI Bus Protocol Overview

2,144 views

3 months ago