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55 results

MSU-IIT Microelectronics Lab
FPGA RFID Door Lock Project | DE0-Nano + RC522 + Buzzer + LEDs + Solenoid by Rejel Jem Sumbillo

In this project, I demonstrate an RFID-based door lock system using the DE0-Nano FPGA and the RC522 RFID module.

2:58
FPGA RFID Door Lock Project | DE0-Nano + RC522 + Buzzer + LEDs + Solenoid by Rejel Jem Sumbillo

41 views

6 days ago

Paul K
How to determine How fast your FPGA is

Hey everyone, My name is Dr. Paul Kerstetter, and today I want to talk about a common question: How fast is my FPGA?

29:58
How to determine How fast your FPGA is

23 views

6 days ago

optimizeFirst
Jane Street Doesn’t Use C++ — Here’s Why OCaml Prints Money 💰

Most people think High-Frequency Trading is all C++, but Jane Street trades billions daily using a "niche" language: OCaml. Why?

1:31
Jane Street Doesn’t Use C++ — Here’s Why OCaml Prints Money 💰

1,073 views

4 days ago

Suman Samui
CORDIC Algorithm Explained for FPGA | Basics & Modes | FPGA Project Series

This video is the first part of an FPGA Design Series focusing on the CORDIC (Coordinate Rotation Digital Computer) algorithm ...

13:52
CORDIC Algorithm Explained for FPGA | Basics & Modes | FPGA Project Series

54 views

3 days ago

Ethan
[Programming/Chatting] The usual FPGA thing again

RISC-Q Project: https://www.cs.umd.edu/~xwu/risc-q.html.

2:52:26
[Programming/Chatting] The usual FPGA thing again

12 views

Streamed 5 days ago

Alex Forencich
FPGA Dev Live Stream: [Re]building Corundum, part 3

FPGA development live stream: Tying off some loose ends - getting ping working finally.

31:55
FPGA Dev Live Stream: [Re]building Corundum, part 3

130 views

Streamed 7 days ago

MCSoC Forum
FPGA Implementation of Tiny Transformer Using High-Level-Synthesis for Biomedical Applications

18th IEEE MCSoC 2025 - Regular Presentation.

11:06
FPGA Implementation of Tiny Transformer Using High-Level-Synthesis for Biomedical Applications

59 views

5 days ago

Suman Samui
Memory-Based MAC Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

By the end of this video, viewers will understand how memory, control logic, and arithmetic units are combined in FPGA to build a ...

13:53
Memory-Based MAC Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

103 views

3 days ago

Sly Fox electronics
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)

Building a Full Adder the Smart Way in Verilog! In this video, we design a 1-bit Full Adder using two Half Adders in Verilog HDL, ...

6:27
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)

28 views

1 day ago

RED DMA
DMA Firmware Creation (Beginner Tutorial)

The core concepts of DMA and why it's a game-changer for speed. ✓ Setting up your development environment (tools & software) ...

11:17
DMA Firmware Creation (Beginner Tutorial)

26 views

19 hours ago

Suman Samui
UART Receiver Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

In this second video of the FPGA Design Series, we present a complete implementation of a UART Receiver on FPGA using ...

10:00
UART Receiver Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

107 views

3 days ago

Manohar K
Signal Processing | filt-filt demo | FPGA | Zedboard | Vivado | Matlab | hdlworkflow | verilog

Use matlab hdlworkflow advisor for fpga code generation and programming.

21:06
Signal Processing | filt-filt demo | FPGA | Zedboard | Vivado | Matlab | hdlworkflow | verilog

0 views

6 days ago

ALL ABOUT VLSI
Hamming Code Encoder & Decoder in Verilog | Code Development & Testbench | Part 2

In this video, we move to Part 2 of the Hamming Code Encoder and Decoder project, where we focus on Verilog RTL ...

18:47
Hamming Code Encoder & Decoder in Verilog | Code Development & Testbench | Part 2

89 views

2 days ago

Tech XORT
Implementing Zynq-7000 AXI Interrupt Controller: Step-by-Step Guide

Learn how to master hardware interrupts on the Zynq-7000 SoC! In this video, I take you through the complete flow of ...

4:48
Implementing Zynq-7000 AXI Interrupt Controller: Step-by-Step Guide

0 views

1 day ago

Emilio Martinez III
Industrial-Grade Arithmetic IP Cores in Verilog

In this video, we cover how to use the arithmetic IP cores from Sections 1.1 through 1.3 of the course curriculum. These IP cores ...

12:31
Industrial-Grade Arithmetic IP Cores in Verilog

21 views

3 days ago

VLSI Excellence – Gyan Chand Dhaka
Round Robin Arbiter in System Verilog | Wrap-Around Logic + Self-Checking Testbench

In this video, we design and verify a Round Robin Arbiter using SystemVerilog — a fundamental digital design block used in ...

20:05
Round Robin Arbiter in System Verilog | Wrap-Around Logic + Self-Checking Testbench

26 views

5 days ago

Mithraya Eduverse
HDLBits Complete Practice Series | #5 Problem Solved

Welcome to the HDLBits Complete Practice Series — where we solve 182 Verilog problems step by step, from beginner to ...

0:49
HDLBits Complete Practice Series | #5 Problem Solved

9 views

5 days ago

Semicon Technolabs
Why Design Verification Is the Backbone of Every Chip | DV Demo by Industry Expert

Thinking of a career in VLSI Design Verification (DV) but not sure where to start? This free DV demo by Semicon Technolabs ...

1:19:03
Why Design Verification Is the Backbone of Every Chip | DV Demo by Industry Expert

4 views

5 days ago

Burak Aydın
Prime_Check_DE0CV

FPGA-based Prime Number Checker & RAM Controller implementation on DE0-CV using Verilog.

2:13
Prime_Check_DE0CV

0 views

5 days ago

Mithraya Eduverse
HDLBits Complete Practice Series | #7 Problem Solved

Welcome to the HDLBits Complete Practice Series — where we solve 182 Verilog problems step by step, from beginner to ...

1:04
HDLBits Complete Practice Series | #7 Problem Solved

0 views

4 days ago