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2,275 results

Anas Salah Eddin
21 - Describing Decoders in Verilog

... called it um generic or decoder generic and it contains the generic decoder code or it will contain it okay so first what we need to ...

23:30
21 - Describing Decoders in Verilog

6,310 views

4 years ago

Jonathan - EE Content
2 to 4 , 3 to 8, 4 to 16 and 5 to 32 bit Decoders in SystemVerilog 👀

In this video I have continued from the previous video in which I designed a 2 to 4 bit decoder. The main idea behind development ...

28:52
2 to 4 , 3 to 8, 4 to 16 and 5 to 32 bit Decoders in SystemVerilog 👀

369 views

4 years ago

Metaphysics Computing
2-bit Decoder - Verilog Development Tutorial p.5

Learn what is a 2-bit decoder and how to implement the block diagram on the DE-10 nano and using Quartus Prime. GITHUB: ...

29:29
2-bit Decoder - Verilog Development Tutorial p.5

564 views

3 years ago

ALL ABOUT ELECTRONICS
Decoder Explained | What is Decoder? Applications of Decoder | 5 to 32 Decoder using 3 to 8 Decoders

In this video, what is decoder, different applications of the decoder, and the logic circuit of the decoder are explained.

21:50
Decoder Explained | What is Decoder? Applications of Decoder | 5 to 32 Decoder using 3 to 8 Decoders

518,810 views

3 years ago

0xdf
Packet Decoder [Day 16 - Advent of Code 2021]

Advent of Code 2021 day 16 solution in Python using Dijkstra's algorithm [00:05] Challenge overview [03:45] Solving part 1 ...

48:02
Packet Decoder [Day 16 - Advent of Code 2021]

403 views

4 years ago

Anas Salah Eddin
22 - Describing Encoders in Verilog

... of combinational circuit building blocks and specifically they perform a function that is the opposite of that of a decoder so let me ...

25:56
22 - Describing Encoders in Verilog

4,818 views

4 years ago

Metaphysics Computing
7-Seg Decoder - Verilog Development Tutorial p.11

Learn how to implement a 7-Segment Display Decoder in Verilog on the DE-10 Nano. Source code: ...

45:38
7-Seg Decoder - Verilog Development Tutorial p.11

818 views

3 years ago

VLSI Simplified
RTL Code & Testbench for Combinational and Sequential Circuits | Verilog HDL Tutorial

In this video, we explore how to write RTL code and build testbenches for both Combinational and Sequential digital circuits using ...

45:13
RTL Code & Testbench for Combinational and Sequential Circuits | Verilog HDL Tutorial

57 views

4 weeks ago

RISC-V: From Transistors to AI
Lecture 6: Implementing Digital Decoder in Verilog

In this lecture, we focus on designing and implementing a digital decoder using Verilog. Decoders are essential in translating ...

20:25
Lecture 6: Implementing Digital Decoder in Verilog

717 views

3 years ago

oicy_design 2024
Decoder and its Design in Verilog

Revision on Decoder concept and its example coding using Verilog.

26:11
Decoder and its Design in Verilog

121 views

1 year ago

Concept Guru
Lecture-7 Verilog HDL Decoder & Encoder

Social Media Link (SML) YouTube Link https://www.youtube.com/conceptguru Facebook Link https://www.facebook.com/jpnverma ...

35:14
Lecture-7 Verilog HDL Decoder & Encoder

583 views

5 years ago

VLSI FOR ALL
Basics of VERILOG | Half & Full Subtractor, Decoder, Encoder, Mux, DeMux with Verilog Code | Class-6

Basics of VERILOG | Half & Full Subtractor, Decoder, Encoder, Mux, De-Mux with Verilog Code | Class-6 Best VLSI Courses ...

41:47
Basics of VERILOG | Half & Full Subtractor, Decoder, Encoder, Mux, DeMux with Verilog Code | Class-6

12,313 views

2 years ago

DVRBLACKTECH
Verilog 5 two to four decoder - verilog - handson - fpga

EDA PLAYGROUND + for more and Verilog FREE course: https://dvrblacktech.000webhostapp.com/dvrCourses.htm.

22:26
Verilog 5 two to four decoder - verilog - handson - fpga

31 views

5 years ago

ALL ABOUT VLSI
VERILOG CODE FOR 4*1 MUX AND 2*4 DECODER WITH TEST BENCH || VERILOG FULL COURSE || DAY 27

vlsi #allaboutvlsi #10ksubscribers #subscribe #verilog.

23:15
VERILOG CODE FOR 4*1 MUX AND 2*4 DECODER WITH TEST BENCH || VERILOG FULL COURSE || DAY 27

271 views

1 year ago

Derek Johnston
Implementing a 5-to-32 Line Decoder in Verilog

In this video, we will work through the entire process of designing and implementing a 5-to-32 Line Decoder in Verilog. We'll start ...

57:19
Implementing a 5-to-32 Line Decoder in Verilog

5,033 views

5 years ago

Sanjay Vidhyadharan
VLSI SYSTEMS AND ARCHITECTURE: Applications of Decoder, Encoder and Multiplexer in Xilinx Verilog

Verilog Codes for 3 X 8 Decoder with Enable, 8 X 3 Encoder and The Multiplexer. Encoder and Decoder Application, Binary to ...

23:55
VLSI SYSTEMS AND ARCHITECTURE: Applications of Decoder, Encoder and Multiplexer in Xilinx Verilog

580 views

3 years ago

Chessda Uttraphan
Multiplexers and Decoders with Verilog HDL

UTHM Online Lecture Faculty of Electrical and Electronic Engineering Universiti Tun Hussein Onn Malaysia.

1:10:45
Multiplexers and Decoders with Verilog HDL

793 views

4 years ago

Made By Ozzy
Hex Decoder FPGA Essentials 004

FPGA Tutorial Series using Intel Altera DE0-CV Cyclone V FPGA. We are developing a graphics engine for the OpenGL standard ...

29:47
Hex Decoder FPGA Essentials 004

466 views

5 years ago

Ekalavya Projects
Design and Simulation of CRC Encoder and Decoder using Verilog

The increasing demand for communication system and storage systems in the modern world there can be errors such as soft ...

35:27
Design and Simulation of CRC Encoder and Decoder using Verilog

881 views

1 year ago

VLSI Simplified
The SHOCKING Truth About Decoders and Priority Mux Exposed

Description: Decoder and Priority Mux in Digital Design | Verilog HDL Implementation In this video, we explore the Decoder and ...

44:30
The SHOCKING Truth About Decoders and Priority Mux Exposed

54 views

2 months ago