computer programming tutorials

The worst optimization a language can have

Some newer languages like Zig and Rust have an "optimization" to change the order of your fields. Unfortunately, this isn't an ...

8:07

The worst optimization a language can have

14,537 views

1 day ago

Chase AI

This Open Source Repo Solves Claude Code's Biggest Problem

Master Claude Code, Build Your Agency, Land Your First Client⚡ https://www.skool.com/chase-ai FREE community ...

10:17

This Open Source Repo Solves Claude Code's Biggest Problem

9,131 views

19 hours ago

PawelCodeStuff

Nginx will finally make sense after this video

Today's video is about Nginx and how it works under the hood. Hope you enjoy! Please let me know in the comments what topic ...

8:21

Nginx will finally make sense after this video

6,548 views

19 hours ago

Systemverilog Academy

Course: Systemverilog Design - 2 : L7.1 : Interfaces in RTL Design Coding

Course: Systemverilog Design 2: Features for RTL Design Coding in SV over Verilog Course ...

3:36

Course: Systemverilog Design - 2 : L7.1 : Interfaces in RTL Design Coding

205 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Design - 1 : L7.2 : Using 'case' statement in RTL Design

Course: Systemverilog Design 1: Assignment Statements & Synthesis in SV Course Playlist: ...

1:05

Course: Systemverilog Design - 1 : L7.2 : Using 'case' statement in RTL Design

201 views

9 hours ago

Tech Talkies

How I make UI easily with Lopaka | For Arduino & ESP32

In this video, we explore Lopaka.app, a powerful web-based embedded GUI designer that helps you create OLED, LCD, TFT, and ...

9:14

How I make UI easily with Lopaka | For Arduino & ESP32

609 views

6 hours ago

Systemverilog Academy

Course: Systemverilog Design - 2 : L4.2: Comparing Verilog & Systemverilog Functions

Course: Systemverilog Design 2: Features for RTL Design Coding in SV over Verilog Course ...

1:05

Course: Systemverilog Design - 2 : L4.2: Comparing Verilog & Systemverilog Functions

191 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Design - 2 : L4.3 : Using Task in Systemverilog

Course: Systemverilog Design 2: Features for RTL Design Coding in SV over Verilog Course ...

1:52

Course: Systemverilog Design - 2 : L4.3 : Using Task in Systemverilog

208 views

9 hours ago

Systemverilog Academy

Course : Systemverilog Verification 4 : L3.1 : Constrain the Randomness

Course : Systemverilog Verification 4 : Writing Random TestBench Course Playlist: ...

6:17

Course : Systemverilog Verification 4 : L3.1 : Constrain the Randomness

273 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Design 3 : L4.1 : Writing General Components in RTL Design - Part A

Course: Systemverilog Design 3: A Professional SoC RTL Design Code Walkthrough Course Playlist: ...

5:11

Course: Systemverilog Design 3 : L4.1 : Writing General Components in RTL Design - Part A

232 views

9 hours ago

Better Stack

This Might Be the Best Claude Code Plugin Right Now (ponytail)

Ponytail is a Claude Code plugin that makes your AI agent think like the laziest senior dev in the room and that's a compliment.

10:07

This Might Be the Best Claude Code Plugin Right Now (ponytail)

15,454 views

8 hours ago

Systemverilog Academy

Course : UVM in Systemverilog 2 : L5.4 : Writing AXI Write Date & Write Response Agent Classes

Course : UVM in Systemverilog 2: Writing Reusable UVM Agents Course Playlist: ...

9:37

Course : UVM in Systemverilog 2 : L5.4 : Writing AXI Write Date & Write Response Agent Classes

137 views

9 hours ago

Systemverilog Academy

Course : Systemverilog Verification 4 : L7.2 : Randsequence part B

Course : Systemverilog Verification 4 : Writing Random TestBench Course Playlist: ...

4:32

Course : Systemverilog Verification 4 : L7.2 : Randsequence part B

215 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Design - 2 : L8.3 : Conditional Generate Statements

Course: Systemverilog Design 2: Features for RTL Design Coding in SV over Verilog Course ...

1:44

Course: Systemverilog Design - 2 : L8.3 : Conditional Generate Statements

144 views

9 hours ago

Systemverilog Academy

Course : Systemverilog Verification 3 : L5.4 : Using the keyword 'super'

Course : Systemverilog Verification 3 : Object Oriented Programming in SV Course Playlist: ...

2:47

Course : Systemverilog Verification 3 : L5.4 : Using the keyword 'super'

270 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Foundations: L12.2 : Simulation Example: Multiplexer

Course: Systemverilog Foundations: Write Your First Design & TB Modules Course Playlist: ...

3:18

Course: Systemverilog Foundations: L12.2 : Simulation Example: Multiplexer

302 views

9 hours ago

Systemverilog Academy

Course: Systemverilog Foundations: L5.5 : Arrays & Operators in Systemverilog

Course: Systemverilog Foundations: Write Your First Design & TB Modules Course Playlist: ...

3:43

Course: Systemverilog Foundations: L5.5 : Arrays & Operators in Systemverilog

385 views

9 hours ago

Systemverilog Academy

Course : UVM in Systemverilog 1: L7.2 : Writing First UVM Transaction & Sequence Classes

Course : UVM in Systemverilog 1: Quick Start for Absolute Beginners Course Playlist: https://www.youtube.com/playlist?list...

11:41

Course : UVM in Systemverilog 1: L7.2 : Writing First UVM Transaction & Sequence Classes

434 views

9 hours ago

Systemverilog Academy

Course : Systemverilog Verification 5 : L14.1 : Summary

Course : Systemverilog Verification 5 : Functional Coverage Coding Course Playlist: ...

1:32

Course : Systemverilog Verification 5 : L14.1 : Summary

119 views

9 hours ago

Perfology

How DoorDash Handles 100TB Logs Daily with OpenTelemetry

How DoorDash processes 100TB of logs daily using scalable OpenTelemetry pipelines for logs, metrics, and traces. Learn how ...

21:25

How DoorDash Handles 100TB Logs Daily with OpenTelemetry

674 views

13 hours ago

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