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Arm®
The AXI Protocol

The Advanced eXtensible Interface (AXI) protocol is a point-to-point interface specification for masters and slaves. This video ...

0:47
The AXI Protocol

39,757 views

5 years ago

FPGAs for Beginners
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

Hi, I'm Stacey, and in this video I discuss AXI! Here's part 2 https://youtu.be/y0z5Cg4gp6k Github Code ...

17:40
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

37,634 views

2 years ago

Dillon Huff
What is AXI (Part 1)

In this video I give a brief overview of the AXI protocol.

7:04
What is AXI (Part 1)

113,908 views

6 years ago

Renzym Education
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]

AXI #AXIstream #AXIMM AMBA AXI Memory Mapped and AXI streaming Interfaces. AXI MM and AXI streaming interfaces are ...

18:56
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]

26,064 views

3 years ago

People also watched

VLSI Technology
[VLSIE003] Bài 2C - Giao thức AMBA APB4 | Logic Design Flow

Video này nằm trong chuỗi bài nói về quy trình thiết kế một lõi IP trong thiết kế số (VLSIE003). Trong chuỗi bài này, các bạn sẽ ...

49:58
[VLSIE003] Bài 2C - Giao thức AMBA APB4 | Logic Design Flow

3,846 views

4 years ago

composer
AXI Verification IP TestBench
14:56
AXI Verification IP TestBench

7,257 views

4 years ago

VerifSudha
Master AXI protocol: AXI WRITE 2 Byte length (4KB crossing)

Have you ever come across phrases like 'A burst must not cross a 4KB address boundary' or 'write transactions with the same ...

11:51
Master AXI protocol: AXI WRITE 2 Byte length (4KB crossing)

7,833 views

2 years ago

Noah De Los Santos
Vivado Tutorial: Turn Verilog IP into AXI Module

This video describes an overview of how I converted my Verilog IP into an AXI module in Vivado so I could test my design.

29:24
Vivado Tutorial: Turn Verilog IP into AXI Module

10,557 views

5 years ago

FPGA Developer
Creating a custom AXI-Streaming IP in Vivado

How to create a custom AXI-Streaming IP in Vivado - useful when you need to get your data from the FPGA fabric and into the ...

14:27
Creating a custom AXI-Streaming IP in Vivado

31,724 views

3 years ago

FPGAPS
Xilinx MIG DDR3 Interface: Read and Write using AXI traffic Generators

Read and write data to the external DDR3 using MIG and Axi Traffic generator. The presenter walks through the entire process ...

8:36
Xilinx MIG DDR3 Interface: Read and Write using AXI traffic Generators

3,176 views

7 months ago

Maikon Nascimento
Using Debugging System ILA with AXIS DMA and FIFO

explaining how to use System ILA to debug AXI4-Stream.

26:04
Using Debugging System ILA with AXIS DMA and FIFO

13,179 views

7 years ago

Microelectronic Systems Design Research Group
AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

The Xilinx ZYNQ Training Video-Book, will contain a series of Videos through which we will make the audience familiar with the ...

1:52:36
AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

121,351 views

11 years ago

Engineering Loop
AXI BUS Protocol || AXI AMBA Protocol || AXI Protocols || AXI AHB APB || AXI Protocols Concept ||

AXI #axiprotocol #busprotocol #amba #iit #nit #mtech AXI BUS Protocol || AXI AMBA Protocol || AXI Protocols || AXI AHB APB ...

1:29:32
AXI BUS Protocol || AXI AMBA Protocol || AXI Protocols || AXI AHB APB || AXI Protocols Concept ||

1,284 views

5 months ago

MASTER VLSI
AXI PROTOCOL - 2

The AXI (Advanced eXtensible Interface) protocol is a standard for high-performance communication between components within ...

1:55:13
AXI PROTOCOL - 2

10,654 views

1 year ago

SiliconAdda
Introduction to Axi4

#Axi protocol #axi #Axi4 #vlsiprojects #vlsi #vlstudies #vlsitraining #amba #Arm #design verification #amba #arm #digital design ...

41:27
Introduction to Axi4

6,975 views

1 year ago

ALL ABOUT VLSI
Introduction to AXI Protocol | AXI Channels Explained | In-Order vs Out-of-Order Transactions

In this video, we dive into the AXI (Advanced eXtensible Interface) Protocol, one of the most widely used AMBA bus protocols in ...

19:52
Introduction to AXI Protocol | AXI Channels Explained | In-Order vs Out-of-Order Transactions

3,887 views

1 month ago

ALL ABOUT VLSI
AXI Protocol Explained: Signal and Channel Descriptions | AXI Read & Write Channels Made Easy

In this video, we'll dive deep into the AXI (Advanced eXtensible Interface) protocol — focusing on signal descriptions and channel ...

26:43
AXI Protocol Explained: Signal and Channel Descriptions | AXI Read & Write Channels Made Easy

1,549 views

1 month ago

FPGAs for Beginners
AXI Stream basics for beginners! A Stream FIFO example in Verilog.

Hi, I'm Stacey, and in this video I go over the basics of the AXI stream interface. HDLforBeginners Subreddit!

12:11
AXI Stream basics for beginners! A Stream FIFO example in Verilog.

45,802 views

4 years ago

Semi Design
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program

Points of XI that is removed for xi4 and some new things were added okay so before that okay let me start with XI protocol and its ...

47:57
AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program

9,644 views

1 year ago

ALL ABOUT VLSI
AXI Write and Read Transfer | Beginner-Friendly AMBA Protocol Tutorial || All about VLSI ||

In this video, we break down the basic Write and Read Transfer operations in the AMBA and AXI protocols, two of the most widely ...

25:16
AXI Write and Read Transfer | Beginner-Friendly AMBA Protocol Tutorial || All about VLSI ||

1,015 views

1 month ago

Electronics & VLSI Projects
What is AMBA - AXI part 1

axi #amba_axi #amba #vlsi #system_verilog #system-verilog #uvm #system-verilog-coding #vlsi_design_verification #verilog We ...

9:05
What is AMBA - AXI part 1

26,530 views

5 years ago

Arm®
The AXI Protocol in a multi-master system design

A System on Chip (SoC) with multiple masters can be configured to use the AXI protocol to define the signals and timing of the ...

1:38
The AXI Protocol in a multi-master system design

17,235 views

5 years ago