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97 results

MSU-IIT Microelectronics Lab
FPGA RFID Door Lock Project | DE0-Nano + RC522 + Buzzer + LEDs + Solenoid by Rejel Jem Sumbillo

In this project, I demonstrate an RFID-based door lock system using the DE0-Nano FPGA and the RC522 RFID module.

2:58
FPGA RFID Door Lock Project | DE0-Nano + RC522 + Buzzer + LEDs + Solenoid by Rejel Jem Sumbillo

41 views

6 days ago

optimizeFirst
Jane Street Doesn’t Use C++ — Here’s Why OCaml Prints Money 💰

Most people think High-Frequency Trading is all C++, but Jane Street trades billions daily using a "niche" language: OCaml. Why?

1:31
Jane Street Doesn’t Use C++ — Here’s Why OCaml Prints Money 💰

1,075 views

4 days ago

Emilio Martinez III
Is This FPGA / ASIC Course Right for You? | Full Course Overview

This video serves as the official introduction to the True Sight Labs FPGA / Front-End ASIC Design Course. In this video, I explain: ...

5:38
Is This FPGA / ASIC Course Right for You? | Full Course Overview

11 views

2 days ago

Suman Samui
CORDIC Algorithm Explained for FPGA | Basics & Modes | FPGA Project Series

This video is the first part of an FPGA Design Series focusing on the CORDIC (Coordinate Rotation Digital Computer) algorithm ...

13:52
CORDIC Algorithm Explained for FPGA | Basics & Modes | FPGA Project Series

54 views

3 days ago

Paul K
How to determine How fast your FPGA is

Hey everyone, My name is Dr. Paul Kerstetter, and today I want to talk about a common question: How fast is my FPGA?

29:58
How to determine How fast your FPGA is

23 views

7 days ago

MCSoC Forum
Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board...

18th IEEE MCSoc 2025 - Regular Presentation.

10:11
Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board...

12 views

7 days ago

Alex Forencich
FPGA Dev Live Stream: [Re]building Corundum, part 3

FPGA development live stream: Tying off some loose ends - getting ping working finally.

31:55
FPGA Dev Live Stream: [Re]building Corundum, part 3

132 views

Streamed 7 days ago

MCSoC Forum
FPGA Implementation of Tiny Transformer Using High-Level-Synthesis for Biomedical Applications

18th IEEE MCSoC 2025 - Regular Presentation.

11:06
FPGA Implementation of Tiny Transformer Using High-Level-Synthesis for Biomedical Applications

59 views

5 days ago

MCSoC Forum
A Review of FPGA-Driven LLM Acceleration

18th IEEE MCSoC 2025 - Regular Presentation.

10:42
A Review of FPGA-Driven LLM Acceleration

70 views

4 days ago

Suman Samui
UART Receiver Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

In this second video of the FPGA Design Series, we present a complete implementation of a UART Receiver on FPGA using ...

10:00
UART Receiver Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

107 views

3 days ago

GeekDot
ATW800/2 runs DOOM?

This is a *demo* of what is possible when using the _virtual_ Transputer built into the ATW800/2 FPGA (called "Seurat").

4:22
ATW800/2 runs DOOM?

471 views

1 day ago

Tech XORT
Implementing Zynq-7000 AXI Interrupt Controller: Step-by-Step Guide

Learn how to master hardware interrupts on the Zynq-7000 SoC! In this video, I take you through the complete flow of ...

4:48
Implementing Zynq-7000 AXI Interrupt Controller: Step-by-Step Guide

0 views

1 day ago

Suman Samui
Memory-Based MAC Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

By the end of this video, viewers will understand how memory, control logic, and arithmetic units are combined in FPGA to build a ...

13:53
Memory-Based MAC Implementation on FPGA using Verilog | Basys-3 | FPGA Design Series

103 views

3 days ago

Ethan
[Programming/Chatting] The usual FPGA thing again

RISC-Q Project: https://www.cs.umd.edu/~xwu/risc-q.html.

2:52:26
[Programming/Chatting] The usual FPGA thing again

12 views

Streamed 5 days ago

Sly Fox electronics
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)

Building a Full Adder the Smart Way in Verilog! In this video, we design a 1-bit Full Adder using two Half Adders in Verilog HDL, ...

6:27
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)

28 views

1 day ago

Pixel Cherry Ninja
FPGA & Retro Gaming News Ep178 | Operation Wolf, Analogue 3D | MiSTer, Analogue Pocket & More

Support the Channel https://www.patreon.com/PixelCherryNinja Find all sources mentioned in the video here ...

18:21
FPGA & Retro Gaming News Ep178 | Operation Wolf, Analogue 3D | MiSTer, Analogue Pocket & More

2,666 views

4 days ago

Manohar K
Signal Processing | filt-filt demo | FPGA | Zedboard | Vivado | Matlab | hdlworkflow | verilog

Use matlab hdlworkflow advisor for fpga code generation and programming.

21:06
Signal Processing | filt-filt demo | FPGA | Zedboard | Vivado | Matlab | hdlworkflow | verilog

0 views

6 days ago

Emilio Martinez III
Industrial-Grade Arithmetic IP Cores in Verilog

In this video, we cover how to use the arithmetic IP cores from Sections 1.1 through 1.3 of the course curriculum. These IP cores ...

12:31
Industrial-Grade Arithmetic IP Cores in Verilog

21 views

3 days ago

RED DMA
DMA Firmware Creation (Beginner Tutorial)

The core concepts of DMA and why it's a game-changer for speed. ✓ Setting up your development environment (tools & software) ...

11:17
DMA Firmware Creation (Beginner Tutorial)

28 views

22 hours ago

Maharshi Sanand Yadav T
create generated clock | short 19 |  create_generated_clock | #sdc #constraints #synthesis #sta

Stay Connected with Me: Become a TMSY Community Member: https://www.youtube.com/@maharshisanandyadav/join ...

1:00
create generated clock | short 19 | create_generated_clock | #sdc #constraints #synthesis #sta

0 views

1 hour ago